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1 ? fn8150.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-352-6832 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. x80070, x80071, x80072, X80073 hot swap controller with advanced fault protection and voltage regulator output features ? hot swap controller ? overvoltage and undervoltage protection ? undervoltage lockout for battery/redundant supplies ? electronic circuit breaker ? slew rate for extern al fet gate control ? overcurrent detection and gate shut-off ? 3x overcurrent limit on insertion ? 5s overcurrent filter ? hardshort retry and indicator ? typically operates from -30v to -80v. tolerates tran- sients to -200v (limited by external components) ? positive voltages (low side switching) from 12v to 60v ? soft re-insertion ? soft extraction ? battery backup mode ? hardshort retry ? overcurrent filter ? insertion limits. ? selectable gate current ? voltage regulator output for supervisory functions ? debounced manual reset input ? available packages ? 20-lead quad no-lead frame (qfn) applications ? -48v hot swap power backplane/distribution central office, ethernet for voip ? positive voltage hotswap 12v to 60v applications (low side switching) ? card insertion detection ? ip phone applications ? databus power interfacing ? custom industrial power backplanes ? distributed power systems description the x80070 is a hot swap contro ller that allows a board to be safely inserted and removed from a live backplane without turning off the main power supply. during insertion, the gate of an external power mosfet is clamped low to suppress contact bounce. the undervoltage/overvoltage circ uits and the power-on reset circuitry suppress the gate turn on until the mechanical bounce has ended. the x80070 turns on the gate with a slew rate to limit the inrush current and incorporates an electronic circuit breaker set by a sense resistor. after the load is successfully charged, the pwrgd signal is asserted; indicating that the device is ready to power sequence the dc-dc power bricks. at all times, the x80070 monito rs for undervoltage, overvoltage, and overcurrent conditions. if an y fault occurs, the gate will be immediately shut off and the pwrgd will be returned to the inactive state. the x80070 contains overvoltage, undervoltage and overcurrent detection, hards hort retry, gate control slew rate and power good control. typical application v dd x80070 v uv/ov v ee sense uv=43v ov=75v -48v gate rs 0.02 ? 5% r4 182k 1% r5 30k 1% r6 10k 1% q1 irfr120 dc-dc module 1 on/off pwrgd 100 22k 3.3n 100n v rgo i gq1 i gq0 gate current select -48v return * * * * optional components depends on choice of dc-dc module data sheet march 15, 2005
2 fn8150.0 march 15, 2005 ordering information absolute maximum ratings temperature under bias ..............................-65c to +135c storage temperature .... .............. .............. ...-65c to +150c voltage on given pin (hot side functions): v ov / uv pin ............................................................ 5.5v + v ee sense pin ...................................................... 400mv + v ee v ee pin .......................................................................... -80v pwrgd pin........................................................... 7 v + v ee gate pin.............................................................. v dd + v ee far pin .................................................................. 7v + v ee mr pin ................................................................. 5.5v + v ee batt-on pin....................................................... 5.5v + v ee voltage on given pin (cold side functions): igq1 and igq0 pins............................................ 5.5v + v ee v dd pin ................................................................. 14v + v ee d.c. output current ........................................................ 5ma lead temperature (soldering, 10 seconds) ..................300c comment stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional oper ation of the device (at these or any other conditions above those listed in the operational sections of this specificati on) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions order number ov (v) uv1 (v) uv2 (v) t nf (us) v oc (mv) v oci (mv) over- current retry retry delay (ms) i gate (ua) t delay (ms) t por (ms) temp part mark x80070q20i 74.9 42.4 33.2 5 50 150 always 100 50 100 100 -40 o c to 85 o c 80070i x80071q20i 68.0 42.4 33.2 5 50 150 always 100 50 100 100 -40 o c to 85 o c 80071i x80072q20i 74.9 42.4 33.2 5 50 150 5 retries 100 50 100 100 -40 o c to 85 o c 80072i X80073q20i 68.0 42.4 33.2 5 50 150 5 retries 100 50 100 100 -40 o c to 85 o c 80073i qfn package (top view) igq1 mr v rgo dnc igq0 dnc na dnc gate na v uv/ov sense far pwrgd batt-on v dd dnc dnc dnc v ee 1 2 3 4 5 678 910 11 12 13 14 15 16 17 18 19 20 5mm x 5mm temperature min. max. industrial -40c +85c supply voltage v dd = 12v x80070, x80071, x80072, X80073
3 fn8150.0 march 15, 2005 electrical characteristics (standard settings) (over the recommended operating conditions unless otherwise specified). symbol parameter min. typ. max. unit test conditions dc characteristics v dd supply operating range 10 12 14 v i dd supply current 2.5 5 ma v rgo regulated 5v output 4.5 5.5 i rgo = 10ua i rgo v rgo current output 50 a i gate gate pin current 46.2 52. 5 58.8 a gate drive on, v gate = v ee , v sense = v ee (sourcing) 9mav gate - v ee = 3v v sense -v ee = 0.1v (sinking) v gate external gate drive (slew rate con- trol) v dd -1 v dd vi gate = 50ua v pga power good threshold (pwrgd high to low) 0.9 1 1.1 v referenced to v ee v uv1 < v uv/ov < v ov v ihb voltage input high (batt-on) v ee + 4 v ee + 5 v v ilb voltage input low (batt-on) v ee + 2 v i li input leakage current (mr , igq0, igq1) 10 a v il = gnd to v cc i lo output leakage current (pwrgd ) 10 a gate is off v il input low voltage (mr , igq0, igq1) -0.5 + v ee (v ee + 5) x 0.3 v v ih input high voltage (mr , igq0, igq1) (v ee + 5) x 0.7 (v ee + 5) + 0.5 v v ol output low voltage (far , pwrgd ) v ee + 0.4 v i ol = 4.0 ma (v ee + 2.7 to v ee + 5.5v) i ol = 2.0 ma (v ee + 2.7 to v ee + 3.6v) c out (1) output capacitance (far )8pfv out = 0v c in (1) input capacitance (mr ) 6 pf v in = 0v v oc overcurrent threshold 45 50 55 mv v oc = v sense - v ee v oci overcurrent threshold (insertion) 135 150 165 mv v oc = v sense - v ee pwrgd = high initial power-up condition v ovr overvoltage threshold (rising) x80070, x80072 x80071, X80073 3.85 3.49 3.90 3.54 3.95 3.59 v referenced to v ee v ovf overvoltage threshold (falling) x80070, x80072 x80071, X80073 3.82 3.46 3.87 3.51 3.92 3.56 v referenced to v ee v uv1r undervoltage 1 threshold (rising) 2.19 2.24 2.29 v referenced to v ee batt-on = v ee v uv1f undervoltage 1 threshold (falling) 2.16 2.21 2.26 v v uv2r undervoltage 2 threshold (rising) 1.71 1.76 1.81 v referenced to v ee batt-on = v rgo v uv2f undervoltage 2 threshold (falling) 1.68 1.73 1.78 v ac characteristics t foc sense high to gate low 1.5 2.5 3.5 s x80070, x80071, x80072, X80073
4 fn8150.0 march 15, 2005 notes: (1) this parameter is based on characterization data. equivalent a.c. output load circuit a.c. test conditions t fuv undervoltage conditions to gate low 0.5 1.0 1.5 s t fov overvoltage conditions to gate low 1.0 1.5 2 s t vfr overvoltage/undervoltage failure re- covery time to gate =1v. 1.2 1.6 2 sv dd does not drop below 3v, no other failure conditions. t batt-on delay batt-on valid 100 ns t mr minimum time high for reset valid on the mr pin 5 s t mre delay from mr enable to gate pin low 1.0 1.6 2.4 si gate = 60a, no load t mrd delay from mr disable to gate reaching 1v 1.8 2.6 si gate = 60a, no load t qc delay from igq1 and igq0 to valid gate pin current 1 s t sc_retry delay between retries 90 100 110 ms t nf noise filter for overcurrent 4.5 5 5.5 s t dpor device delay before gate assertion 45 50 55 ms input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 output load standard output load electrical characteristics (standard settings) (continued) (over the recommended operating conditions unless otherwise specified). symbol parameter min. typ. max. unit test conditions 5v 4.6k ? 30pf far pwrgd x80070, x80071, x80072, X80073
5 fn8150.0 march 15, 2005 figure 1. overvoltage/undervoltage gate timing figure 2. overcurrent gate timing figure 3. manual reset sense v uv/ov v ov v uv v dd v th mr gate v oc v oci t vfr t fov t fuv t dpor t vfr 1v 1v sense v dd v th gate v oc v oci t dpor t sc_retry t foc t foc always retry v uv < v uv/ov < v ov t sc_retry mr = high t mrd gate t mre mr t mr 1v x80070, x80071, x80072, X80073
6 fn8150.0 march 15, 2005 typical performance characteristics overcurrent threshold vs. temperature overvoltage threshold vs. temperature undervoltage 1 threshold vs. temperature undervoltage 2 threshold vs. temperature i gate (source) vs. temperature i gate (sink) vs. temperature 46.000 47.000 48.000 49.000 50.000 51.000 52.000 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature inrush current limit (mv) 3.85 3.86 3.87 3.88 3.89 3.90 3.91 3.92 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature rising falling ov threshold (v) 2.190 2.200 2.210 2.220 2.230 2.240 2.250 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature rising falling undervoltage 1 threshold (v) 1.690 1.700 1.710 1.720 1.730 1.740 1.750 1.760 1.770 1.780 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature rising falling undervoltage 2 threshold (v) 0 40 80 120 160 200 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature 150a 70a 50a 10a gate current (a) 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature gate current - sink (ma) x80070, x80071, x80072, X80073
7 fn8150.0 march 15, 2005 t fuv vs. temperature t fov vs. temperature t foc vs. temperature 0.500 0.550 0.600 0.650 0.700 0.750 0.800 -55-40-25-10 5 203550658095110125 temperature tuv1 tuv2 t uv (s) 1.0 1.1 1.1 1.2 1.2 1.3 1.3 1.4 1.4 -55-40-25-10 5 203550658095110125 temperature t ov (s) 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature t oc (s) x80070, x80071, x80072, X80073
8 fn8150.0 march 15, 2005 figure 4. block diagram sense v ee gate igq1 igq0 batt-on mr v dd far pwrgd power good logic slew rate selection 5v reg v rgo v ee v ee v ov ref v uv1 ref v uv2 ref v uv/ov 2:1 mux v ee gate control v dd v oc ref 38r 3r reset logic and delay v ee overcurrent logic, hard short relay, retry logic status and delay por timing/ control logic 50ua x80070, x80071, x80072, X80073
9 fn8150.0 march 15, 2005 pin configuration functional description hot circuit insertion when circuit boards are inserted into a live backplane, the bypass capacitors at the input of the board?s power module or dc/dc converter can draw huge transient currents as they charge up. this transient current can cause permanent damage to the board?s components and cause transients on the system power supply. the x80070 is designed to turn on a board?s supply voltage in a controlled manner (see figure 5), allowing the board to be safely inserted or removed from a live backplane. the device also provides undervoltage, overvoltage and overcurrent protection while keeping the power module (dc-dc converter) off until the backplane input voltage is stable and within tolerance. figure 5. typical inrush with gate slew rate control pin descriptions pin name description 1v rgo regulated 5v output. used to pull-up user programmable in puts igq0, igq1, batt-on and mrh (if needed). 2dnc pin not used. do not connect to this pin. 3na2 not available. connect to v ee . 4na2 not available. connect to v ee . 5v dd positive supply voltage input. 6v ee negative supply voltage input. 7v uv/ov analog undervoltage and overvoltage input. turns off the external n-channel mosfet when there is an undervoltage or overvoltage condition. 8sense circuit breaker sense input . this input pin detects the overcurrent condition. 9gate fet gate drive. this pin supplies the cur- rent to turn on the fet. 10 dnc pin not used. do not connect to this pin. 11 dnc pin not used. do not connect to this pin. 12 na1 not available. connect to v rgo . 13 na1 not available. connect to v rgo . 14 na2 not available. connect to v ee . 15 far failure after re-try (far ) output signal. 16 batt-on battery on input . this input signals that the battery backup (or secondary supply) is supplying power to the backplane. it has an internal pulldown resistor. (>10m ? typical) 17 pwrgd power good output. this output pin en- ables a power module. x80070 20l qfn package igq1 mr v rgo dnc igq0 na2 na1 dnc gate na1 v uv/ov sense far pwrgd batt-on v dd na2 dnc na2 v ee 1 2 3 4 5 678 910 11 12 13 14 15 16 17 18 19 20 top view na1 pins connect to v rgo 5mm x 5mm na2 pins connect to v ee 18 igq1 gate current quick select bit 1 input. this pin is used to change the gate current drive and is intended to allow for current ramp rate control of the gate pin of an external fet. it has an internal pulldown resistor. (>10m ? typical) 19 igq0 gate current quick select bit 0 input. this pin is used to change the gate current drive and is intended to allow for current ramp rate control of the gate pin of an external fet. it has an internal pulldown resistor. (>10m ? typical) 20 mr manual reset. pulling the mr pin low initiates a gate pin reset (gate pin pulled low). the mr signal must be held low for 5 secs (minimum). pin descriptions (continued) pin name description v gate v fet_drain pwrgd i inrush x80070, x80071, x80072, X80073
10 fn8150.0 march 15, 2005 figure 6. typical -48v hotswap application circuit overvoltage and undervoltage shutdown the x80070 provides overvoltage and undervoltage protection circuits. when an overvoltage (v ov ) or undervoltage (v uv1 and v uv2 ) condition is detected, the gate pin immediately pulls low turning off the supply to the system. the undervoltage threshold v uv1 applies to the normal operation with a main supply. the undervoltage threshold v uv2 assumes the system is powered by a battery. when using a battery backup, the batt-on pin is pulled to v rgo . the default thresholds have been set so the external resistance values in figure 6 provide an overvoltage threshold of 74.9v (x80070 and x80072) or 68v (x80071 and X80073), a main undervoltage threshold of 43v and a battery undervoltage threshold of 33.8v. as shown in figure 9, this circ uit block contains comparators and voltage references to monitor for a single overvoltage and dual undervoltage trip points. the overvoltage and undervoltage trip points as shown in table 1 below. table 1. overvoltage/undervoltage default thresholds a resistor divider connected between the plus and minus input voltages and the v uv/ov pin (see figure 7) determines the overvoltage and undervoltage shutdown voltages and the operating voltage range. using the thresholds in table 1 and the equations of figure 7 the de sired operating voltage can be determined. figure 8 shows the resistance values for various operating voltages (x80070 and x80072). figure 7. overvoltage undervoltage divider figure 8. operating voltage vs. resistor ratio battery back up operations an external signal, batt-on is provided to switch the undervoltage trip point. the batt-on signal is a logic high if v ihb > v ee + 4v and is a logic low if v ilb < v ee + 2v. the time from a batt-on input change to a valid new undervoltage threshold is 100ns. see electrical specifications for more details. note: the v uv/ov pin must be limited to less than v ee + 5.5v. in worst case conditions. values for r1 and r2 must be chosen such that this condition is met. intersil recommends r1 = 182k ? and r2 = 10k ? to conform to factory settings. these should be 1% resistors. table 2. selecting between undervoltage trip points threshold symbol description falling rising max/min voltage 1 lockout voltage 2 v ov overvoltage (x80070/72) 3.87v 3.9v 74.3 74.9 v ov overvoltage (x80071/73) 3.51v 3.54v 67.4 68 v uv1 undervoltage 1 2.21v 2.24v 43.0 42.4 v uv2 undervoltage 2 1.73v 1.76v 33.8 33.2 notes: 1: max/min voltage is the maximum and mimimum operating voltage assuming the recommended v uv/ov resistor divider. 2: lockout voltage is the voltage where the x8007x turns off the fet. v dd x80070 v uv/ov v ee sense -48v uv=43v ov=75v/72v -48v gate rs 0.02 ? 5% r4 182k 1% r5 30k 1% r6 10k 1% q1 irfr120 return -48v dc/dc converter i inrush pwrgd on/off v rgo 100n 100 22k 3.3n 100uf 10k pin description trip point selection batt-on undervoltage trip point selection pin if batt-on = 0, v uv1 trip point is selected; if batt-on = 1, v uv2 trip point is selected. v uv1 and v uv2 are undervoltage thresholds. r1 r2 v p v uv/ov v n voltage divider: or: v uv ov ? v s r2 r1 r2 + ---------------------- ?? ?? = v s v uv ov ? r1 r2 + r2 ---------------------- ?? ?? = v s batt-on = v ee v ov v uv1 v uv2 operating voltage batt-on = v rgo 100 90 80 70 60 50 40 30 20 10 0 150 158 166 175 182 190 198 206 214 222 operating voltage (volts) r1 in k ? (for r2=10k) x80070, x80071, x80072, X80073
11 fn8150.0 march 15, 2005 figure 9. overvoltage/undervoltage for primary and battery backup overcurrent protection (circuit breaker function) the x80070 overcurrent circuit provides the following functions: ? overcurrent shut-down of the power fet and external power good indicators. ? noise filtering of the current monitor input. ? relaxed overcurrent limits for initial board insertion. ? overcurrent recovery retry operation. overcurrent shut-down a sense resistor, placed in the supply path between v ee and sense (see figure 6) generates a voltage internal to the x80070. when this voltage exceeds 50mv, an overcurrent condition exists and an internal ?circuit breaker? trips, turning off the gate drive to the exter nal fet. the actual overcurrent level is dependent on the value of the current sense resistor. for example a 20m ? sense resistor sets the overcurrent level to 2.5a. as shown in figure 10, this over current circuit block contains a resistor ladder, a comparator, a noise filter and a voltage reference to monitor for overcurrent conditions. the overcurrent voltage threshold (v oc ) is 50mv. this can be factory set, by special order, to any setting between 30mv and 100mv. if an overcurrent condition is detected, the gate output is shut down and the power good indicator goes inactive. overcurrent during insertion insertion is defined as the first plug-in of the board to the backplane. in this case, the x80070 is initially fully powered off prior to the hot plug connection to the main supply. this condition is different from a si tuation where the main supply has temporarily failed result ing in a partial recycl e of the power. this second condition will be referred to as a power cycle. during insertion, the board can experience high levels of current for short periods of time as power supply capacitors charge up on the power bus. to prevent the overcurrent sensor from turning off the fet inadvertently, the x80070 has the ability to allow more current to flow through the power fet and the sense resistor for a short pe riod of time until the fet turns on and the pwrgd signal goes active. in the x80070, 150mv is allowed across sense resistor during insertion (7.5a assuming a 20mw resistor). this provides a mechanism to reduce insertion issues associated with huge current surges. insertion currents of 1x, 2x, or 4x are also available. please contact intersil for these factory options. after the pwrgd signal is asserted, the x80070 switches back to the normal overcurrent setting. hardshort protec tion - (retry) in the event on an overcurrent or hard short condition, the x80070 includes a retry circuit. this circuit waits for 100ms, then attempts to again turn on the fet. if the fault condition still exists, the fet turns off and the sequence repeats. for versions x80070 and x80072, th is process continues indefinely until the overcurrent condition does not exist. for the x80071 and X80073, this process repeats five times only, then will keep the fet off and set the far pin active. after far is asserted, it can be cleared using the master reset pin, mr , or cycling the power-on v dd . when using the mr pin, the far output is cleared upon mr assertion. if an overcurrent condition does not occur on any retry, the gate pin will proceed to open at the user defined slew rate. figure 10. overcurrent detection/short circuit protection. overcurrent noise filter the x80070 has a noise (low pass) filter built into the overcurrent comparator. the co mparator will thus require the current spikes to exceed the overcurrent limit for more than 5s. voltage voltage 2:1 mux voltage -48v v uv/ov batt-on r1 r2 v uv1 v uv2 to gate to gate + - + - + - v ov reference reference reference control control 25k 450k overcurrent/ gate short-circuit retry logic retry voltage 5us noise 38r 3r + ? -48v overcurrent event r sense reference delay control bl ock filtering x80070, x80071, x80072, X80073
12 fn8150.0 march 15, 2005 gate drive output slew rate (inrush current) control the gate output drives an exte rnal n-channel fet. the gate pin goes high when no overcurrent, undervoltage or overvoltage conditions exist. the x80070 provides an i gate current of 50ua to provide on- chip slew rate control to minimize inrush current and provide the best turn on time for a given load, while avoiding overcurrent conditions. slew rate (gate) control as shown in figure 11, this circuit block contains a current source (i gate ) that drives the 50ua current into the gate pin. this current provides a controlled slew rate for the fet. to give the designer flexibilit y in the design of the hot swap circuit, the x80070 provides two external pins, igq1 and igq0. these pins allow the user to switch to different gate currents on-the-fly by selecting one of four pre-selected i gate currents. when igq0 and igq1 are left unconnected, the gate current is 50ua. the other three settings are 10ua, 70ua and 150ua, as shown in table 3. typically, the delay from igq1 and igq0 selection to a change in the gate pin current is less than 1 second. figure 11. slew rate (inrush current) control gate capacitor, filtering and feedback the fet control circuit includes an fet feedback capacitor c 2 , which provides compensation for the fet during turn on. the capacitor value depends on the load, the choice of fet (because of the fet internal capacitances) and the fet gate current. the value of c2 can be selected with the following formula. where: i gate = fet gate current i inrush = maximum desired inrush current c load = dc/dc bulk capacitance with the x80070, there is some control of the gate current with the igq pins, so one selection of c2 can cover a wide range of possible loading conditions. typical values for c2 range from 2.2 to 4.7nf. when power is applied to the syst em, the fet tries to turn on due to its internal gate to drain capacitance (cgd) and the feedback capacitor c2 (see fi gure 11.) the x80070 device, when powered, pulls the gate output low to prevent the gate voltage from rising and keep the fet from turning on. however, unless v dd powers up very quickly, there will be a brief period of time during initial application of power when the x80070 circuits cannot hold the gate low. the use of an external capacitor (c1) prevents this. capacitors c1 and c2 form a voltage divider to prevent the gate voltage from rising above the fet turn on threshold before the x80070 can hold the gate low. use the following formula for choosing c1. where: v1 = maximum input voltage, v2 = fet threshold voltage, c1 = gate capacitor, c2 = feedback capacitor. in a system where v dd rises very fast, a smaller value of c1 may suffice as the x80070 will control voltage at the gate before the voltage can rise to the fet turn on threshold. the circuit of figure 11 assumes that the input voltage can rise to 80v before the x80070 sees operational voltage on v dd . if c1 is used then the series resistor r1 will be required to revent high frequency oscillations. power good indication the pwrgd signal asserts (logic low) only when all of the below conditions are true: ? there is no overvoltage or no undervoltage condition, (i.e. undervoltage < v ee < overvoltage.) ? there is no overcurrent condition (i.e. v ee - v sense < v oc .) ? the fet is turned on (i.e. v gate > v dd - 1v) table 3. igq gate current selection igq1 pin igq0 pin operation 0 0 defaults to gate current 50 a 0 1 gate current is 10 a 1 0 gate current is 70 a 1 1 gate current is 150 a sense v ee r sense load rds on v dd i.e. 12v slew rate logic gate 50a i inrush gate select logic igq1 igq0 -48v current 100 100n 22k 3.3nf c1 c2 r2 r1 c2 i gate c load i inrush ------------------------------------------- = c1 v1 v2 ? v2 --------------------- c 2 = x80070, x80071, x80072, X80073
13 fn8150.0 march 15, 2005 as shown in figure 12, this circuit block contains a comparator, and an internal voltage reference. these provide a circuit to determine the whether the gate drive to the fet has fully turned on as requested. if so, the power good indicator (pwrgd ) goes active. figure 12. power good indicator manual reset the x80070 has a manual reset pin. mr (manual reset). the mr signal is used as a manual reset for the gate pin. this pin is used to initiate soft reinsert. when mr is pulled low the gate pin will be pulled low. it also clears the far signal. when the mr pin goes high, it removes the override signal and the gate will turn on based on the selected gate control mechanism. (see figure 3.) table 4. manual reset (gate signal) v ee r sense gate power logic load pwrgd v dd - 1v -48v good output drive ref overvoltage good signal undervoltage good signal overcurrent good signal mr gate pin requirements 1 operational when mr is high the reset function is disabled 0offmr must be held low minimum of 5 secs x80070, x80071, x80072, X80073
14 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8150.0 march 15, 2005 packaging information 20-lead quad flat no lead package (package code: q20) 5mm x 5mm body with 0.65mm lead pitch note: 1. the package outline drawing is compa- tilbe with jedec mo-220; variations: whhc-2, except dimensions d2 and e2. 2. the terminal #1 identifier is a laser marked feature symbols dimensions in millimeters min nom max a 0.70 0.75 0.80 a1 0.00 0.02 0.05 b 0.25 0.30 0.35 a3 0.19 0.20 0.25 d 4.90 5.00 5.10 d2 3.70 3.80 3.90 e 4.90 5.00 5.10 e2 3.70 3.80 3.90 e ? 0.65 ? l 0.35 0.40 0.45 y ? 0.08 pin 1 indent e d a a1 e2 d2 b e a3 l c y c x80070, x80071, x80072, X80073

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